Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a latency control circuit capable of allowing latency information to be reflected in an input signal and outputting a signal in which the latency information has been reflected.
In general, a semiconductor memory device such as a DDR is SDRAM (Double Data Rate Synchronous DRAM) may set various portions of latency information and perform a predetermined circuit operation according to the latency information. CAS latency is one example of latency information used in a semiconductor memory device. The CAS latency defines a time that elapses until data is outputted after a read command is inputted, and the semiconductor memory device may output data at a desired time point by using the CAS latency after the read command. That is, the semiconductor memory device performs a shifting operation based on the CAS latency after the read command, and outputs data in response to a shifted output signal. Thus, the data is outputted in response to the time point, at which the CAS latency is reflected, after the read command.
Meanwhile, in addition to DDR SDRAM, other semiconductor devices also use latency information that performs a function similar to that of the CAS latency. In the present specification, circuits controlled in response to such latency information will be defined as a latency control circuit.
FIG. 1 is a block diagram illustrating a general latency control circuit.
Referring to FIG. 1, the latency control circuit generates an output signal OUT according to latency information INF_LAT<5:10> and an input signal IN, and includes a clock synchronization block 110 and a selection output block 120.
The clock synchronization block 110 shifts an input signal IN in response to a clock signal CLK, and includes first to tenth clock synchronization units 110_1 to 110_10 that output an inputted signal in synchronization with the clock signal CLK. The first clock synchronization unit 110_1 outputs the input signal IN in synchronization with the clock signal CLK, and each of the second to tenth clock synchronization units 110_2 to 110_10 outputs an output signal of a previous clock synchronization unit in synchronization with the clock signal CLK.
The selection output block 120 selects an output signal from the output signals of the fifth to tenth clock synchronization units 110_5 to 110_10 according to the latency information INF_LAT<5:10>, and outputs the selected output signal.
FIG. 2 is a timing diagram illustrating the circuit operation of the latency control circuit illustrated in FIG. 1. For the purpose of convenience, it is assumed that the latency information ‘INF_LAT<8>’ of the latency information INF_LAT<5:10> is activated to a high level. This represents that the output signal OUT is activated corresponding to the time point at which the clock signal CLK is toggled eight times after the input signal IN is activated.
Referring to FIGS. 1 and 2, if the input signal IN is activated to a signal having a high-level pulse width, the first clock synchronization unit 110_1 outputs the input signal IN as a first output signal N1 in synchronization with the clock signal CLK. The second clock synchronization unit 110_2 outputs the first output signal N1 as a second output signal N2 in synchronization with the clock signal CLK. The third to tenth clock synchronization units 110_3 to 110_10 perform the same operation as that of the second clock synchronization unit 110_2. That is, the third to tenth clock synchronization units 110_3 to 110_10 output signals, which are inputted thereto, as the third to tenth output signals N3 to N10 in synchronization with the clock signal CLK, respectively.
Since the selection output block 120 selects an eighth output signal N8 in response to the latency information ‘INF_LAT<8>’ of the latency information INF_LAT<5:10>, the output signal OUT of the selection output block 120 is the eighth output signal N8.
As can be seen from FIGS. 1 and 2, the latency control circuit performs a shifting operation with respect to the input signal IN in synchronization with the clock signal CLK, selects a signal corresponding to the latency information INF_LAT<5:10> of the shifted signals as the output signal OUT, and outputs the output signal OUT. As a result, the output signal OUT represents the input signal IN shifted according to the latency information INF_LAT<5:10>.
As described above, the general latency control circuit performs the shifting operation, and receives the clock signal CLK which is toggled for the shifting operation. The first to tenth clock synchronization units 110_1 to 110_10 receiving the clock signal CLK perform the shifting operation according to the toggling of the clock signal CLK. By performing a shifting operation in this manner power is consumed by each of the first to tenth clock synchronization units 110_1 to 110_10.